Solid state light sources, such as light emitting diodes (LEDs) can be used in a variety of lighting devices, products, components, and/or fixtures for general commercial and personal lighting applications. Advantages of using LED products include an increase in energy savings and product lifetimes. For example, when LED chips or LEDs are used as the light source in components or fixtures for downlighting, backlighting, and general illumination applications, the components advantageously consume less energy than those using conventional filament light bulbs, metal halide high-intensity discharge (HID), and compact fluorescent light (CFL) bulbs.
LEDs are currently utilized in devices or packages for providing white light (e.g., perceived as being white or near-white), and are developing as replacements for incandescent, fluorescent, and metal halide high-intensity discharge (HID) devices. A representative example of an LED device comprises a device having at least one LED, a portion of which can be coated with a phosphor such as, for example, yttrium aluminum garnet (YAG). The phosphor coating can convert light emitted from one or more LEDs into white light. LEDs can emit light having desired wavelengths, and phosphor can in turn emit yellow fluorescence with a peak wavelength of about 550 nm, for example. A viewer perceives the mixture of light emissions as white light. As an alternative to phosphor converted white light, light emitting devices of red, green, and blue (RGB) wavelengths can be combined in one device or package to produce light that is perceived as white.
Traditional high quality LEDs and wirebonds can have a low failure rate on a chip by chip basis. However, the failure rate generally increases proportionally to the number of LEDs used within a given device, for example, in an LED array. For example, one high quality LED can have a 1-ppm failure rate which can increase to a 100-ppm failure rate when 100 LEDs are used in a device or component comprising a 100 LED array. This failure rate can prove unacceptably high for consumers of LED products, and may result in the catastrophic failure of devices and components incorporating LED arrays and/or a large number of LEDs within the device or component. In one aspect, a catastrophic failure of the device or component can occur where a plurality of LEDs within the device fail to emit light and/or one or more regions or areas of an LED array fail to emit light, or emit light that is substantially non-uniform.
FIG. 1A schematically illustrates a first connection method for a conventional LED array, generally designated 10. FIG. 1B is a circuit diagram of the LED array configured according to FIG. 1A. The first connection method disclosed by FIGS. 1A and 1B includes a plurality of LEDs electrically connected in series or strings between two terminals, where the series are then electrically connected in parallel between the two terminals. For example, first and second electrically conductive traces or terminals 12 and 14, also known as “bus bars” are provided which can supply electrical current to one or more LEDs 16. First and second terminals 12 and 14 can comprise electrically conductive areas or layers of material, for example, areas or layers of copper (Cu) configured to have opposing electrical polarity. First and second terminals 12 and 14 can be disposed on a mounting substrate or submount (not shown), such as a dielectric laminate, printed circuit board (PCB), or metal core printed circuit board (MCPCB). One of the first and second terminals 12 and 14, respectively, comprises an anode and the other a cathode. In one aspect, first terminal 12 comprises an anode and second terminal 14 comprises a cathode such that electrical signal or current can flow downwardly (e.g., from terminal 12 towards terminal 14, as illustrated) through the strings of LEDs 16. First and second terminals 12 and 14 can electrically communicate with a power source (not shown) which can be integrally disposed within a device incorporating LED array 10, or disposed in an external driver or driving circuit. In most cases, LEDs 16 are driven using a constant current power source.
As noted above, FIG. 1A illustrates the first connection method for producing conventional LED arrays, which comprises electrically connecting LEDs 16 in series or strings between first and second terminal 12 and 14, respectively, where the strings are parallel to each other between the terminals. LEDs 16 can be mounted to an electrically and/or conductive mounting area disposed on the substrate or submount (not shown, e.g., a mounting area of a dielectric laminate, PCB, MCPCB, etc.) such as for example, an area of Cu. Each series or string can comprise LEDs 16 electrically connected directly to each other via one or more electrically conductive connectors, such as wirebonds 18. In one aspect, wirebonds 18 comprising gold (Au) or other conductive filament can be configured for transferring electrical signal from first terminal 12, to each of the LEDs 16 within the string, where it can exit the string at the second terminal 14. In conventional arrangements, each LED 16 within a string is limited in electrical communication to at most two other LEDs 16 (or electrical component(s) such as terminals 12 and 14) via a direct wirebond 18 connection. That is, conventional LEDs 16 have two substantially small bond pads as described further below, where a first bond pad facilitates a direct electrical connection to a first adjacent LED and a second bond pad facilitates a direct electrical connection to a second adjacent LED via wirebonds 18. For illustration purposes, array 10 is illustrated as comprising four LEDs 16 electrically connected in series disposed between first and second terminals 12 and 14, where four strings are electrically connected in parallel (e.g., a 4×4 array 10). However, arrays can be formed via the first connection method using any number of strings electrically connected in parallel, and any number of LEDs 16 per string.
The first connection method illustrated by FIGS. 1A and 1B can have advantages, such as including a fewer number of wirebonds (i.e., fewer objects to block or interfere with light emission), a fewer number of design features on a mounting substrate or submount, more flexible LED arrangements upon the mounting submount (e.g., multiple ways to arrange LEDs 16 on a large, open submount), better packing density, and brighter devices in general due to less obstructions. However, this connection method has several disadvantages and can be susceptible to catastrophic failure where at least one LED 16 fails during operation. That is, conventional LEDs and conventional connecting methods can be highly sensitive to individual chip failures such that failure of as little as one LED 16 could cause LED array 10 to catastrophically fail. For example and in one aspect, LED 16 failure modes “open” or “short” LEDs 16 and can be characterized by the LEDs 16 failing to emit light when exposed to electrical current. Such failure modes can be attributed to handling defects occurring during manufacture of the LED 16 and/or array 10, defects in the electrical connection between adjacent LEDs 16 within the array 10 (e.g., broken wirebond 18), and/or defects internal the device (e.g., defects within the individual LED structure or build). LEDs 16 which go open (i.e., no current flowing through the LED 16) can cause other LEDs 16 within array 10 to take on more electrical current that becomes diverted away from the defected open LED 16. In some instances, the increased current can overload other LEDs 16 within array 10, and cause a portion of the other LEDs 16 to fail. LEDs 16 which go short (i.e., leaky LED 16) can consume more current thereby pulling in current intended for other LEDs 16 within array 10 (e.g., diverting current away from other LEDs 16 in array 10), thereby causing one or more LEDs 16 to become dim in comparison to the defective short LED. Short LEDs typically eventually go open, which can then divert current away from other LEDs 16 with array 10, and cause a portion of the other LEDs 16 to fail. Thus, short and/or open LEDs 16 occurring in the first conventional connection method (i.e., strings in parallel) can cause array 10 to catastrophically fail during operation because of a single, individual LED 16 failure. Array 10 can be highly sensitive to individual LED 16 failure rate.
The circuit diagram of FIG. 1B illustrates the effect of an open LED 16 within array 10, where the array comprises one or more strings of serially connected LEDs 16 electrically connected in parallel between first and second terminals 12 and 14, respectively. For example, incoming electrical current, designated I, can be supplied from a constant current power source and flow between first and second terminals 12 and 14. Typically, current I can be evenly distributed between the number of columns or strings within a given array. For example and as FIG. 1B illustrates, current I can be evenly distributed to the first through fourth columns of array 10 where current flowing to the first column or string is designated IC1, current flowing to second column or string is designated IC2, current flowing to third column or string is designated IC3, and current flowing to fourth column or string is designated IC4 (and so on where there are more than four columns). A defective LED or LED chip, generally designated D, is disposed in the first column and is assumed to have gone open because of a broken wirebond or other defect. As a result, no current IC1 can flow through defective chip D. Current IC1 must therefore be diverted away from the first column into other adjacent strings or columns as designated by the arrows. That is, current from first string IC1 can become diverted to other strings IC2, IC3, and IC4 and can result in an increased current to those strings, the increased current denoted IC2+, IC3+, and IC4+. As a result, none of the other LEDs 16 within the first string below D can receive current or therefore function or illuminate because of open defective chip D. As such, the first string will have only one functioning LED 16. The initial currents IC2, IC3, and IC4 of the first through fourth strings can increase to IC2+, IC3+, and IC4 + by an amount expressed as C/(C−1) where C is the total number of columns or strings per array. The second, third and fourth LEDs 16 in the second through fourth strings can comprise increased currents IC2+, IC3+, and IC4+ until exiting array via terminal 14, and as such, the majority of the second through fourth strings will be brighter than normal and the majority of the first string will be dark.
Depending upon the design and the number of columns or strings in array 10, this can cause a catastrophic failure of array 10 or device incorporating array 10 where current to other strings becomes too much and overloads or overburdens LEDs 16 within the other strings. For example, where a small number of strings are present (e.g., C<3) in array 10, the diverted current may be as much as two times the amount of current that the string is configured to receive. This can cause failure of the remaining string(s) within array 10 in addition to the string with the open or defective chip D. Thus, LEDs 16 within the one or more strings would fail to illuminate, and array 10, or a device incorporating array 10, would be at least partially if not totally dark thereby resulting in a catastrophic failure of array 10 as a result of the original defective chip D.
In instances where defective chip D is a short (not shown) as opposed to an open device, the initial currents IC2, IC3, and IC4 become diverted from strings containing normally functioning LEDs 16 to the first string containing the short, or leaky defective chip D. As a result, IC1 increases because more current is consumed by leaky LED chip D. The increased current can cause each of the LEDs 16 within the first string containing defective chip D to become bright compared to LEDs 16 of remaining strings (e.g., illuminated by a current reduced or diverted from IC2, IC3, and IC4). Depending upon the design, this type of failure generally poses catastrophic failure risk for arrays comprising two or more strings of LEDs (e.g., C>2), as the defective string could take on as much as two or more times the amount of current it is configured to receive. This type of failure typically results in the leaky or short defective chip D finally going open, and the catastrophic failure of one or more strings of array 10 as described in FIG. 1B could result based upon the single defective chip D. However, where a large number of rows are present and because voltage increases with respect to current, other strings may continue to consume some of the current and array 10 would exhibit non-uniform and/or partially darkened illumination, which is also undesirable. Notably, for either failure mode, array 10 can catastrophically fail because of a single, individual short or open defective LED chip D, and as the number of LEDs 16 increases, the probability of defective chips D increases.
FIG. 2 schematically illustrates a conventional LED 16 which may be used in conventional arrangements or arrays of LEDs as described in FIGS. 1A, 1B (and 3A and 3B, see below). LED 16 can comprise one or more external sides 20 which can be straight-cut (i.e., substantially vertical) or beveled (i.e., substantially angled) between upper and lower surfaces of LED 16. Sides 20 of LED 16 can be substantially equal in length or can vary in length and therefore be configured to form different shapes, for example, a rectangular as illustrated. LED 16 can be fabricated on growth substrates (such as a SiC or sapphire substrate) to provide horizontal devices (i.e., with both electrical contacts on a same side of the LED) or vertical devices (i.e., with electrical contacts on opposite sides of the LED). Notably, LED 16 is limited to a direct connection with at most two other structures, for example, adjacent LEDs 16, terminals 12, 14, and/or bus bars 32 (FIGS. 3A and 3B). That is, conventional LED 16 cannot electrically communicate directly with more than two other electrical components (e.g., other LEDs, terminals, etc.) via wirebonds. As FIGS. 1A and 3A illustrate, wirebonds 18 can extend from at most two sides 20 of LED 16 and can extend in opposite directions from opposite sides 20 such that wirebonds 18 are substantially linearly aligned along a same line.
In one aspect, LED 16 can comprise a horizontal build having two electrical contacts or bond pads on the same surface of LED 16. For example, LED 16 can comprise first and second bond pads 22 and 24 of electrically opposite polarity disposed on the upper surface of LED 16. In one aspect, first bond pad 22 can comprise an anode and second bond pad 24 can comprise a cathode, where each bond pad 22 can be comprised of Au or other conductive material. Each bond pad 22 and 24 is adapted to electrically connect to at most one other adjacent LED 16. LED 16 can further comprise an active area 26 which illuminates when electrical current passes through the LED 16 via bond pads 22 and 24. In one aspect, active area 26 can comprise an InGaN junction disposed on a thermally conductive silicon carbide (SiC) substrate. Active area 26 can extend under and/or around bond pads 22 and 24 such that a portion of active area 26 is adjacent to each side 20 of the device. In one aspect, active area 26 can extend to each edge 20 uniformly, such that the length between active area 26 and each edge 20 is the same or substantially the same distance X. In one aspect, active area 26 can extend within approximately 20 μm of each edge. That is, active area 26 (along each side 20) can be approximately 40 μm smaller in overall length than each respective edge 20.
In one aspect, bond pads 22 and 24 are relatively small compared to the overall size of LED 16, as bond pads 22 and 24 are adapted to bond or electrically communicate with at most one other LED 16 or electrical component via only one wirebond 18. For example, in one aspect, first bond pad 22 can be approximately 90 μm in diameter and second bond pad 24 can be approximately 98 μm in diameter. Each bond pad 22 and 24 can comprise an area that can be approximately 5% or less than the overall chip area (calculated based on a chip having a length and width of approximately 350 μm×470 μm). Larger LEDs would have similarly sized bond pads 22 and 24 as described herein (to accommodate similarly sized wirebonds 18), thus the percentage of bond pad to overall chip area would continue to decrease below approximately 5% for larger LEDs 16. In one aspect, first bond pad 22 can comprise approximately 4% of chip area and second bond pad 24 can comprise approximately 5% of overall chip area 26 (e.g., calculated based upon a chip having a length and width of approximately 350 μm×470 μm). Thus when taken together, first and second bond pads 22 and 24 occupy approximately 9% of the overall chip area of LED 16. A current spreading structure 28 can spread current thereby distributing heat across LED 16 during operation to increase brightness by allowing LEDs 16 to run cooler. Current spreading structure 28 may also prevent failures of LEDs 16 due to thermal stresses or reduce heat related failure modes.
FIG. 3A schematically illustrates a second conventional connection method for a conventional LED array, generally designated 30. FIG. 3B is a circuit diagram for LED array 30 configured according to FIG. 3A. The second connection method disclosed by FIGS. 3A and 3B includes a series and parallel arrangement, where rows and columns are tied together at each LED chip or LED 16. That is, LED array 30 comprises four rows of LEDs 16 and four columns of LEDs 16 (e.g., a 4×4 array) disposed between first and second terminals 12 and 14. LEDs 16 of each row can be electrically connected in parallel between a terminal and intervening bus bar 32 and/or between a pair of intervening bus bars 32, where each row can be electrically connected in series with the preceding and/or subsequent row. That is, LEDs 16 within each column are serially connected via wirebonding to intervening bus bars 32 provided between the rows. This can produce a more robust array 30 in terms of failure modes attributed to open and short LEDs such as defective LED chips D, as each column and row can become less sensitized to the failure of a single defective chip D.
As illustrated, each LED 16 electrically connects directly to bus bars 32 and/or terminals 12 and 14 via wirebonds 18 as opposed to a direct electrical connection to another adjacent LED 16. First and second terminals 12 and 14 as well as intervening bus bars 32 can comprise electrically conductive areas of material, for example, areas or layers of Cu. Terminals 12 and 14 can be configured to have opposing electrical polarity. Terminals 12 and 14 and bus bars 32 can be disposed on a mounting substrate or submount (not shown), such as a PCB, MCPCB, or dielectric laminate structure. With respect to electrical polarity, intervening bus bars 32 can be configured to electrically connect LEDs in series and parallel between first and second terminals 12 and 14. Accordingly, intervening bus bars 32 can alternate in electrical polarity depending upon the arrangement of LEDs 16.
The circuit diagram of FIG. 3B illustrates the effect of an open LED within array 30, where array 30 comprises rows of LEDs 16 electrically connected in parallel, and where each row electrically connects in series via an electrical connection to intervening bus bars 32. For example, incoming electrical current, designated I, can be supplied from a constant current power source and flow between first and second terminals 12 and 14. Typically, current I can be evenly distributed between the number of columns within a given array. For example and as FIG. 3B illustrates, current I can be evenly distributed to the first through fourth columns of array 30 where current flowing to the first column is designated IC1, current flowing to second column is designated IC2, current flowing to third column is designated IC3, and current flowing to fourth column is designated IC4 (and so on where there are more than four columns). A defective LED or LED chip, generally designated D, is disposed in the second row of first column and is assumed to have gone open because of a broken wirebond or other defect. As a result, no initial current IC1 can flow through defective chip D, where chip is open. Current IC1 can be diverted from chip D into other LEDs 16 within the same row (i.e., LEDs 16 in adjacent columns electrically connected in parallel with chip D) as illustrated by the arrows. That is, array 30 allows current to be directed around the defective chip D such that current IC1 thereby increases current of adjacent LED 16 as indicated by IC2+, IC3+, and IC4+. The increased currents IC2+, IC3+, and IC4+ can only affect LEDs 16 within the same, single row as defective chip D, as current can redistribute evenly through the four columns IC1, IC2, IC3, and IC4 beginning with the next row (i.e., third row). This can be achieved because intervening bus bar 32 can effectively push current IC1 back into LEDs 16 within the same column as defective chip D. As a result, none of the other LEDs 16 within the same and/or adjacent rows or columns as defective chip D will lose current. Only defective chip D fails to illuminate, thereby increasing the ability of array 30 to better withstand catastrophic failure due to one defective LED chip D. However, catastrophic failure may still result as described below.
When defective chip D is open, the initial currents IC2, IC3, and IC4 for LEDs 16 with the same row can increase to IC2+, IC3+, and IC4+ by an amount expressed as C/(C−1) where C is the total number of columns per array. Only LEDs 16 in the same row as defective chip D may be forced to undergo the higher current, and the other chips in the same column continue to function. Depending upon the design and the number of columns in array 30, this can cause a catastrophic failure of array 30 or lighting device incorporating array 30 where current to LEDs 16 within the same row as defective chip D becomes too much and overloads or overburdens the LEDs 16 in the same row as defective chip D. For example, where a small number of columns are present (e.g., C<3) in array 30, the diverted current may be as much as two times the amount of current that LEDs 16 within that row are configured to receive. This can cause failure of the LEDs 16 within the second row along with the open or defective chip D. Thus, LEDs 16 within the one or more rows would fail to illuminate, and array 30, or a device incorporating array 30, would be at least partially if not totally dark thereby resulting in a catastrophic failure as a result of the original defective chip D. Notably, array 30 which is comprised of the second connection method is more robust but still susceptible to catastrophic failure. Disadvantages of this connection method include more wirebonds (e.g., more light obstruction) and other disadvantages attributed to stationary or fixed intervening bus bars 32, for example, a reduction in mounting area available to mount LEDs 16 (e.g., because of space reserved for intervening bus bars 32). The size and permanent location of bus bars 32 further negatively affects or discourages flexible chip arrangements and the packing density of LEDs 16 within array 30. Moreover, bus bars 32 are electrical connections which are fixedly disposed on a mounting submount, which further limits LED configurations or arrangements over the submount.
In instances where defective chip D is a short (e.g., leaky LED, not shown) as opposed to an open device, more current can become diverted to chip D and other LEDs 16 within that same row (i.e., second row) to accommodate the defective chip D. Defective chip D and LEDs 16 within the same row can conduct less and become dim compared to other LEDs 16 in array 30. Depending upon the design, this type of failure generally poses catastrophic failure risk for arrays comprising two or more columns of LEDs (e.g., C>2), as the defective chip D and LEDs 16 within the same row could take on as much as two or more times the amount of current that the devices are configured to receive. This type of failure typically results in the leaky or short defective chip D finally going open, and LEDs 16 in remaining rows quickly progressing to catastrophic failure. The progression of events may be less obvious to the user, and may therefore be considered better or more robust to failure.
Despite the availability of various LEDs, devices, and methods in the marketplace, a need remains for making LED arrays more insensitive to individual chip failure rates. A need also remains for LEDs, devices, and methods allowing for more flexible arrangements of LEDs electrically connected in series and/or parallel, where such arrangements do not include one or more large, fixed or stationary bus bars.